Methodology -S2C

Methodology

Chip designers do their best to use the latest cocktail of verification techniques and tools, and EDA companies continually innovate new verification tools, design flows, and pre-verified silicon IP, in a valiant effort to achieve the elusive goal of achieving chip design verification perfection.

Prototyping

High performance and high density
Automatic partitioning
Deep trace debug
Flexible & powerful I/Os

Emulation

High capacity

Simulation

Flexibly design in various ways
Cycle and event driven mode
High speed simulation engine
Advanced modeling interface

Formal

RTL code analysis
Logic equivalent check
Vacuous assertion check
Verification progress and coverage measurement

Modeling

Architecture design
System performance analysis logic equivalent check
Virtual devices
IP modeling in early design stage

Verification Tool Comparison

The increasing size and complexity of SOC/ASIC designs have led to an exponential increase in the complexity of validation. In order to reduce time to market, it is important to choose different verification tools in different design stages to improve efficiency and accelerate the convergence of verification.

All

Simulation

Emulation

Prototyping

Design Verification Process

Architecture Design

IP Development

SoC Integration

System Testing

Tape-out

Architecture Design

Simulation

Emulation

Prototyping

Formal

Heterogeneous Verification

Architecture Design

IP
Development

SoC
Integration

System
Testing

Tape-out

Rapid architecture design & System performance analysis & Software and hardware co-design

Shorten the Design Cycle

Heterogeneous Verification Platform

FPGA-based prototyping tools are scalable, cost-effective for almost any design, offer capable debug visibility, and are well suited to hardware-software co-verification. S2C has researched how the need for co-verification evolved with chip complexity, where FPGAs got their start in verification, and why ASIC design benefits from prototyping technology.

Design architecture planning, system performance analysis, virtualization application scenarios and IP modeling in the early stage
Support SystemVerilog, Verilog and VHDL RTL level simulation
Hardware simulation accelerates super-large design simulation speed and supports automatic compilation and full signal visibility
High-performance prototype verification for early software development and extensive system testing
Use transaction-level interfaces to reduce test program development time while ensuring the accuracy of system results