メソドロジ-S2C：Rapid FPGA-based SoC & ASIC Prototyping

メソドロジ

S2C provides complete design and verification services based on FPGA prototyping. Let S2C's extensive experience and proven results work for you in your next design challenge.

Prototyping

High performance and high density
Automatic partitioning
Deep trace debug
Flexible & powerful I/Os

Emulation

Up to 1 billion ASIC gates
Fast compilation functions
Full visibility
Support ICE/SBA/TBA

Simulation

Flexibly design in various ways
Cycle and event driven mode
High speed simulation engine
Advanced modeling interface

Formal

RTL code analysis
Logic equivalent check
Vacuous assertion check
Verification progress and coverage measurement

Modeling

Architecture design
System performance analysis logic equivalent check
Virtual devices
IP modeling in early design stage

検証ツール比較

The increasing size and complexity of SOC/ASIC designs have led to an exponential increase in the complexity of validation. In order to reduce time to market, it is important to choose different verification tools in different design stages to improve efficiency and accelerate the convergence of verification.

All

Simulation

Emulation

Prototyping

設計と検証のプロセス

Design Verification Process

Architecture Design

IP Development

SoC Integration

System Testing

Tape-out

Architecture Design

Simulation

Emulation

Prototyping

Formal

Heterogeneous Verification

Architecture Design

IP
Development

SoC
Integration

System
Testing

Tape-out

Rapid architecture design & System performance analysis & Software and hardware co-design

Shorten the design cycle

ヘテロジニアス検証プラットフォーム

S2C's Prodigy Prototyping technology provides industry-leading remote management capabilities, ranging from remote FPGA download, virtual IOs, switches, UARTs & LEDs and remote power cycles, to enterprise-class server/client management software, to provide effective resource sharing and management.

Design architecture planning, system performance analysis, virtualization application scenarios and IP modeling in the early stage
Support System Verilog, Verilog, VHDL RTL level simulation
Early simulation verification without a complete RTL design
Hardware simulation accelerates super-large design simulation speed and supports automatic compilation and full signal visibility
High-performance prototype verification for early software development and extensive system testing
Use transaction-level interfaces to reduce test program development time while ensuring the accuracy of system results