S2C Announces a New TAI Verification Module | InfoTECH
Jun 07, 2011

S2C Announces a New TAI Verification Module

 By Meenakshi Shankar 
S2C Inc., a company delivering rapid SoC prototyping solutions since 2003, has made available  a new patent-pending TAI Verification Module, a prototype verification product that allows user designs in FPGA-based prototypes to be verified with massive and fast test benchs through a x4 PCIe Gen2 channel to the PC.

Mon-Ren Chene, S2C's chairman and chief technology officer said in a press release that many of its customers want to transfer large amounts of verification data to and from their FPGA-based prototypes. Chene also mentioned what the company noticed as the limitations of the FPGA vendor tools that allow users to debug one FPGA at a time. This, the company felt to be fine for single FPGA solutions, but is very limiting for multiple FPGA solutions like S2C’s new 32.8 million gate 4 FPGA Quad S4 TAI LM that it released in April 2011.

“We came with the idea for the Verification Module that enables the bi-directional high speed data transfer between the FPGA-based prototype and the user's verification environment using an x4 PCIe Gen 2 channel. The TAI Verification Module also allows the user to simultaneously look at signals from multiple FPGAs," Chene added.

As noted, the Altera (News - Alert) Stratix-4 GX FPGA-based TAI Verification Module has integrated Altera SignalTap Logic Analyzer with S2C's TAI Player software enabling concurrent debugging of multi-FPGA design using the RTL names. The technology is said to support set up of multiple groups of 480 probes during design compilation so the user can view thousands of RTL-level probes in multiple FPGA without requiring lengthy FPGA recompilation.

The S2C S4 TAI Verification Module provides three usage modes: Verification Mode, Debug Mode and Logic Mode. The Verification Mode enables the transfer of large amounts of data from/to a PC through a x4-lane PCIe Gen2 interface using SCE-MI or customizable C-API. In the Debug Mode, the S4 TAI Verification Module enables simultaneous debugging of multiple FPGAs using Altera SignalTap while maintaining the user's RTL net names. The user can prototype a design with capacity up to 3.6M gates in the Logic Mode. All debug and verification setup for the Verification Module is done in the TAI Player Pro software.

The S4 TAI Verification Module can be used as a standalone prototyping board for smaller scale SoC or ASIC design for up to 3.6M gate capacity. The S4 TAI Verification Module can mount either the Altera Stratix IV 180 or 360 GX FPGA and has a total of 480 external I/O on 4 LM connectors, x4 PCIe Gen2 Interface and 2 pairs of Gigabit transceiver through SMA (News - Alert) connectors.

Headquartered in San Jose, California, S2C recently announced that ChipStart will distribute its rapid SoC prototyping products in Canada, New England and Texas. In addition to selling S2C’s products, ChipStart will supply first line applications support too, reported TMC (News - Alert).


ザイリンクス VU440
ザイリンクス KU115
ザイリンクス VU19P
ザイリンクス VU13P
ザイリンクス VU9P
インテル S10-10M
インテル S10-2800
4 つの FPGA
複数の FPGA デバッグ ツール
コモデリング ツール (FPGA と PC ホスト間で大量のデータをやり取りできます)

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