Solving the Next Big SoC Challenges with FPGA Prototyping |
Mar 01, 2016

Solving the Next Big SoC Challenges with FPGA Prototyping

Daniel Nenni  Published on 03-01-2016 03:00 PM

The health of the semiconductor industry revolves around the “start”. Chip design starts translate to wafer starts, and both support customer design wins and product shipments. Roadmaps develop for expanding product offerings, and capital expenditures flow in to add capacity enabling more chip designs and wafer starts. If all goes according to plan, this cycle continues.

Article: Higgs bosons, (un)certainty, and black holes-solving-next-big-soc-challenges-fpga-min-jpg

Unfortunately “all” rarely goes according to plan especially if you are in a competitive market and designing on leading edge processes. This is where FPGA-based prototyping comes in. A complete verification effort has traceable tests for all individual intellectual property (IP) blocks and the fully integrated design running actual software (co-verification) and is far beyond what simulation tools alone can do in reasonable time. Hardware emulation tools are capable and fast, but highly expensive, often out of reach for small design teams. FPGA-based prototyping tools are scalable, cost-effective, offer improved debug visibility, and are well suited for software co-verification and rapid turnaround of design changes. 

Which brings us to this week’s tutorial at DVCON. I hope to see you there:

Solving the Next Big SoC Challenges with FPGA Prototyping and Stratix 10
We’re all too familiar with the fact that large SoC designs present challenges in both design and verification. FPGA prototyping offers obvious advantages for both design and verification but many dismiss the notion of employing FPGA prototyping because of size constraints, hardware scalability, partitioning challenges, performance, debug ability, and in-circuit testing. While previous generations of FPGAs and FPGA prototyping couldn’t tackle large designs, advances in both FPGA and FPGA prototyping technologies and methodologies have given way to breaking through these challenges.

This tutorial will explore the advances of Altera’s Stratix 10 FPGA and the FPGA prototyping techniques and technology that will work with Stratix 10 to accomplish the prototyping of even the largest SoC. Case studies will be provided that will demonstrate how to properly take advantage of Stratix 10 FPGA prototyping for compiling, partitioning, and debugging across multiple devices. 

THURSDAY March 03, 2:00pm - 5:30pm | Sierra
Toshio Nakama - S2C, Inc.
Manish Deo – Intel/Altera Corp.

If you get the chance to meet Toshio after the tutorial I would highly recommend it. He is the Co-founder and CEO of S2C, Inc. and has over 18 years of experience in the electronic design automation industry as well as FPGA architecture and design. Prior to S2C, Toshio held the positions of Asia director of sales and field applications engineering manager at Aptix and worked at Altera. Toshio has an EMBA degree from CEIBS and a BSEE from Cornell University.

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors DVCon Europe and DVCon India. For more information about Accellera, please For more information about DVCon U.S., please visit Follow DVCon on Facebook or @dvcon_us on Twitter or to comment, please use #dvcon_us.


ザイリンクス VU440
ザイリンクス KU115
ザイリンクス VU19P
ザイリンクス VU13P
ザイリンクス VU9P
インテル S10-10M
インテル S10-2800
4 つの FPGA
複数の FPGA デバッグ ツール
コモデリング ツール (FPGA と PC ホスト間で大量のデータをやり取りできます)

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