S2C adds support for Juno ARM dev platform | SemiWiki.com
Oct 19, 2016

S2C adds support for Juno ARM dev platform

Don Dingee  Published on 10-19-2016 02:00 PM

We’ve had several blogs introducing the Juno ARM Development Platform as a vehicle for ARMv8-A software development. S2C has jumped in with a module connecting their FPGA-based prototyping platform to the Juno, enabling more advanced IP block development for ARMv8-A systems.

A quick refresher on the Juno SoC and development board: it’s become the defacto reference platform for software development on ARM Cortex-A57 (or Cortex-A72) and Cortex-A53 big.LITTLE clusters, and a newer version with a Cortex-A72 and Cortex-A53 cluster. It also provides a look at a Mali-T624 GPU and the CCI-400 cache coherent interconnect, along with a DDR3 memory subsystem, an optional PCIe controller, and a Cortex-M3 core for system control functions. 

By tapping into the LogicTile expansion card interface, a daughtercard has access to the Juno SoC via AXI. That provides enough bandwidth to create custom logic on a FPGA. Extending the concept to a full FPGA-based prototyping platform, custom logic can be created and debugged without having to worry about partitioning the processor and GPU cores into FPGAs. The result is a complete ARMv8-A software environment with a validated Linaro port, plus any custom IP in the FPGA-based prototyping platform.

S2C is the latest vendor to get on board with Juno. The Prodigy Juno ARM Interface Module plugs into the Juno board, cabled to a Prodigy Complete Prototyping Platform.

Article: Cooley on Synopsys-EVE-juno-arm-development-platform-connected-s2c-prodigy-logic-module-jpg

S2C is taking the concept a bit farther with a complete, easy to set up reference design supporting either Prodigy Virtex UltraScale or Prodigy Kintex UltraScale Logic Modules in this configuration. The reference design illustrates how self-testing works with the two environments connected together, how FPGA capacity is utilized, how OS kernel and driver code for the ARMv8-A processor works with the FPGA-based prototyping system, and how high-speed DDR4 memory access between the Logic Modules and the Juno ARM Development Platform works.

With more ARMv8-A usage coming on line, especially in server-class applications, prototyping other IP blocks for workload-optimized designs is becoming increasingly important. One of the big set up factors in FPGA-based prototyping is having to partition a large processor cluster into several FPGAs successfully. Using the Juno ARM Development Platform helps avoid that step (at least if stock ARM cores are being used) and reduces the overall time to set up an FPGA-based prototype.

The combined environments also enable the FPGA-based prototyping tools to be used. Better debug capability helps designers test and verify IP blocks more thoroughly. Scalability is also a concern – the S2C environment extends all the way from a single logic module to over 1.5B gates with the Prodigy Cloud Cube architecture.

Article: Cooley on Synopsys-EVE-s2c-prodigy-juno-arm-interface-module-jpg

S2C will be demonstrating the Prodigy Juno ARM Interface Module in booth #915 at ARM TechCon 2016 in Santa Clara next week, stop by if you get a chance. For more details on the Prodigy Juno ARM Interface Module and the Prodigy Complete Prototyping Platform, here’s the full press release:

S2C’s Latest Prodigy Interface Module for Juno ARM Development Platform Speeds FPGA Prototyping and Increases Scalability

It’s cool to see momentum developing around the Juno platform, and I imagine as processor core complexity continues to increase we will see more of this approach from ARM and the FPGA-based prototyping vendors. I also like that ARM isn’t competing with its ecosystem and vendors like S2C, allowing market solutions to take shape.


ザイリンクス VU440
ザイリンクス KU115
ザイリンクス VU19P
ザイリンクス VU13P
ザイリンクス VU9P
インテル S10-10M
インテル S10-2800
4 つの FPGA
複数の FPGA デバッグ ツール
コモデリング ツール (FPGA と PC ホスト間で大量のデータをやり取りできます)

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