HW+SW FPGA-accelerated Prototyping package deals end at Midnight, March 31

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HW+SW FPGA-accelerated Prototyping package deals end at Midnight, March 31 | Xilinx

Jan 30, 2015

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S2C’s FPGA prototyping platform bundles include the company’s ProtoBridge FPGA-accelerated verification and co-modeling software and a SingleE V7 Logic Module or a K7 Logic Module respectively based on a Xilinx Virtex-7 XC7V2000T 3D FPGA or a Xilinx Kintex-7 XC7K410T or XC7K325T FPGA. S2C’s ProtoBridge links system-level simulation environments to FPGA-based prototyping, which:

enables early algorithm/architectural exploration on FPGA-based hardware
accelerates design verification
increases FPGA-based prototyping test coverage

FPGA prototyping platforms are growing in popularity due to their relatively low expense and ability to test system designs much faster than software-based simulation.

S2C SingleE V7 Logic Module.jpg

S2C SingleE V7 Logic Module—based on a Xilinx Virtex-7 XC7V2000T 3D FPGA

S2C K7 Logic Module—based on Xilinx Kintex-7 FPGAs

The company’s ProtoBridge software creates an AXI-based communication bridge between a host-based software modeling and simulation platform and one of the company’s FPGA-based protyping modules. The ProtoBridge software enables designers to read from and write data to their FPGA-mapped ASIC designs, which accelerates algorithm validation, block-level prototyping, full-chip simulation, and corner-case testing. It also permits SoC software development much earlier in the design cycle, which dramatically reduces the verification bottleneck. ASIC designers—especially regular DVcon attendees—already know that verification now consumes the lion’s share of the development cycle.

ASIC Design Flow.jpg

FPGA Prototyping in the ASIC Design Flow

You can use S2C’s ProtoBridge at multiple points in the ASIC Design Flow:

C/C++ test development. ProtoBridge allows you to exercise tests written in C/C++ on an FPGA-based prototype at high speed.
Model development in SystemC. you can then use an OSCI-C simulator to exercise and test these models on an FPGA-based prototype using ProtoBridge.
SystemVerilog verification. Use the SystemVerilog environment to test your ASIC design on FPGA-based prototypes.
Link with third-party ESL tools. S2C’s ProtoBridge has been integrated with Mentor’s Vista and deployed in a number of verification flows. The integration allows the use of mature ESL models, putting part of a design in an FPGA-based prototype.

The ProtoBridge package consists of software and an FPGA design component. The software portion consists of Linux/Windows drivers and a set of C-API/DPI routines that performs AXI transactions over a PCIe Gen2 link to the FPGA hardware module. The FPGA design component contains a PCIe interface block, an interconnection module, and AXI transactors that you instantiate in your DUT (design-under-test). Test programs running on a host can read and write through the APIs at speeds of up to 500Mbytes/sec through the PCIe Gen2 interface.

S2C ProtoBridge Hardware Configuration.jpg